/*
 * Copyright (c) 2023 HiSilicon (Shanghai) Technologies CO., LIMITED.
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef __CMU_CTL_RB_REG_OFFSET_H__
#define __CMU_CTL_RB_REG_OFFSET_H__

/* CMU_CTL_RB Base address of Module's Register */
#define CMU_CTL_RB_BASE (0x4001A000)

/* **************************************************************************** */
/*           HH503 CMU_CTL_RB Registers' Definitions                            */
/* **************************************************************************** */

#define CMU_CTL_RB_DBG_CMU_XO_PD_REG       (CMU_CTL_RB_BASE + 0x400)
#define CMU_CTL_RB_CMU_XO_SIG_REG          (CMU_CTL_RB_BASE + 0x404)
#define CMU_CTL_RB_CMU_CFG0_REG            (CMU_CTL_RB_BASE + 0x408)
#define CMU_CTL_RB_CMU_FNPLL_CFG0_REG      (CMU_CTL_RB_BASE + 0x40C)
#define CMU_CTL_RB_CMU_FNPLL_CFG1_REG      (CMU_CTL_RB_BASE + 0x410)
#define CMU_CTL_RB_CMU_FNPLL_CFG2_REG      (CMU_CTL_RB_BASE + 0x414)
#define CMU_CTL_RB_CMU_FNPLL_CFG3_REG      (CMU_CTL_RB_BASE + 0x418)
#define CMU_CTL_RB_CMU_FNPLL_CFG4_REG      (CMU_CTL_RB_BASE + 0x41C)
#define CMU_CTL_RB_CMU_FNPLL_CFG5_REG      (CMU_CTL_RB_BASE + 0x420)
#define CMU_CTL_RB_CMU_FNPLL_STATE0_REG    (CMU_CTL_RB_BASE + 0x424)
#define CMU_CTL_RB_CMU_FNPLL_STATE1_REG    (CMU_CTL_RB_BASE + 0x428)
#define CMU_CTL_RB_CMU_FNPLL_SIG_REG       (CMU_CTL_RB_BASE + 0x42C)
#define CMU_CTL_RB_CMU_FBDIV_REG           (CMU_CTL_RB_BASE + 0x430)
#define CMU_CTL_RB_CMU_FRAC_REG            (CMU_CTL_RB_BASE + 0x434)
#define CMU_CTL_RB_CMU_CLK_WF_RX_REG       (CMU_CTL_RB_BASE + 0x438)
#define CMU_CTL_RB_CMU_CLK_BT_RX_REG       (CMU_CTL_RB_BASE + 0x43C)
#define CMU_CTL_RB_CMU_CLK_WF_TX_REG       (CMU_CTL_RB_BASE + 0x440)
#define CMU_CTL_RB_CMU_CLK_BT_TX_REG       (CMU_CTL_RB_BASE + 0x444)
#define CMU_CTL_RB_CMU_CLK_320M_WDBB_REG   (CMU_CTL_RB_BASE + 0x448)
#define CMU_CTL_RB_CMU_CLK_480M_WDBB_REG   (CMU_CTL_RB_BASE + 0x44C)
#define CMU_CTL_RB_CMU_CLK_480M_USBDFT_REG (CMU_CTL_RB_BASE + 0x450)
#define CMU_CTL_RB_CMU_CLK_24M_USB_REG     (CMU_CTL_RB_BASE + 0x454)
#define CMU_CTL_RB_CMU_CLKOUT0_REG         (CMU_CTL_RB_BASE + 0x460)
#define CMU_CTL_RB_CMU_CLKOUT1_REG         (CMU_CTL_RB_BASE + 0x464)
#define CMU_CTL_RB_COEX_PTA_SWITCH_CMU_RF_MAN_REG   (CMU_CTL_RB_BASE + 0x470)
#define CMU_CTL_RB_CMU_CFG1_REG            (CMU_CTL_RB_BASE + 0x480)
#define CMU_CTL_RB_PMU_CMU_RB_RST_SEL_REG  (CMU_CTL_RB_BASE + 0x484)

#endif // __CMU_CTL_RB_REG_OFFSET_H__
